A Major Shift in AI Hardware Design

According to industry analysts at SemiAnalysis, Google has partnered with AMD to develop a new version of its Tensor Processing Unit, or TPU, marking a significant shift in how the company approaches artificial intelligence hardware. This collaboration represents AMD’s first major involvement in designing a custom AI accelerator chip, and it suggests Google is moving toward a fundamentally different architecture for handling demanding computing workloads.

For the past nine generations, Google has developed its TPU lineup largely on its own, relying on partners like Broadcom to handle the actual silicon manufacturing. The company has extensive expertise in accelerator architecture and proprietary tensor computing design. So why bring AMD into the picture now? The answer lies in a growing recognition that pure acceleration power is no longer enough for modern AI workloads.

The CPU Factor: A Forgotten Piece of the Puzzle

artificial intelligence processing unit chip
Photo by Igor Omilaev

The key insight driving this partnership centers on something that sounds counterintuitive: AI systems increasingly need general-purpose computing power alongside specialized accelerators. While large language model training has traditionally been dominated by tensor processing, newer AI applications, particularly reinforcement learning for reasoning and autonomous agents, demand significantly more traditional CPU cycles.

Google’s own infrastructure evolution demonstrates this trend. In its latest TPU 8i systems designed for inference and reasoning tasks, the company now pairs one Google Axion CPU with every two TPUs, a much higher ratio than previous generations. Some internal analysis suggests an even more aggressive approach, with a 1:1 ratio of CPUs to accelerators potentially being optimal for future workloads. This represents a fundamental rethinking of AI server architecture.

AMD brings precisely what Google needs for this transition. The company already manufactures a data center accelerator called the Instinct MI300A that combines x86 CPU cores and specialized accelerator chiplets on the same physical package. This experience with hybrid processor design, combined with AMD’s expertise in advanced packaging techniques and CPU instruction set architecture, makes it an ideal partner for integrating CPU resources directly into a TPU product.

What This Means for the Market

cpu processor core technology
Photo by Brian Kostiuk

This development carries important implications for anyone purchasing or deploying AI infrastructure. The shift toward CPU-heavy AI workloads suggests that future systems will require different cost-benefit calculations. Rather than sizing servers around accelerator capacity alone, buyers will need to consider overall compute balance and may find themselves investing in systems with more traditional CPU resources than previous AI deployments required.

The rumored TPU v10 design would integrate CPU cores directly into the accelerator package, reducing the physical distance between general-purpose and tensor computing. This integration can yield meaningful improvements in performance and power efficiency, since data no longer has to travel as far between different components. Bringing AMD’s x86 architecture directly into the TPU package represents a pragmatic solution to an engineering challenge that Google identified within its own infrastructure.

The Broader Context

While this is still speculation based on industry analysis, the implications extend beyond just one product. If Google is indeed moving toward CPU-inclusive accelerators, other chip makers may follow suit. Intel, which has strategic relationships with Google, lacks experience building hybrid CPU and accelerator packages of this type, leaving AMD as a more natural fit for this particular partnership.

The trend also reflects a maturing understanding of what artificial intelligence infrastructure actually needs. Early AI deployments treated accelerators as standalone powerhouses, with general-purpose CPUs relegated to support roles. As demand for CPU resources continues to evolve across computing markets, architects are realizing that reasoning tasks, agentic workloads, and reinforcement learning applications demand a more balanced approach.

For consumers and enterprise buyers evaluating AI infrastructure, this news underscores an important lesson: the specifications that matter for AI workloads keep changing. What qualifies as adequate CPU resources today may prove insufficient tomorrow. Understanding these trends helps inform smarter purchasing decisions when the time comes to upgrade or expand AI computing capacity.