Arm Brings New Details on Its Upcoming Server CPU

At Hot Chips 2026, Arm revealed substantial technical specifications for its AGI data center processor, which will begin shipping in late 2026. The company filled in many blanks about the processor’s architecture, manufacturing approach, and design philosophy. This information matters for buyers evaluating next-generation server infrastructure, particularly those planning deployments around artificial intelligence and advanced workloads.

Core Count and Performance Specifications

computer chip manufacturing process
Photo by Umberto

Arm’s AGI is a dual-chiplet design that delivers either 64, 128, or 136 Neoverse V3 processor cores. Each core runs at clock speeds between 2.80 GHz and 3.70 GHz and features wide front-end processing with ten-wide decode and dispatch capabilities. The processor includes two 128-bit vector engines per core and 2MB of L2 cache per core, plus up to 272MB of system-level cache. Physically, each chiplet contains 70 cores, with four redundant cores built in to boost manufacturing yield rates. Both chiplets are manufactured on TSMC’s N3P process node and are connected via a high-speed UCIe fabric running at 32 GT/s, delivering an aggregate bandwidth of 2 TB/s between the two chiplets.

Unconventional Architecture Choices

Arm’s design diverges from typical approaches used by competitors like AMD, Intel, and Nvidia. Rather than separating compute and I/O onto distinct chiplets, Arm integrated both functions onto each chiplet as a self-contained system. This approach prioritizes memory locality and bandwidth over the modular design practices that dominate the industry. The rationale becomes clear when examining the memory subsystem: by keeping memory controllers on the same die as processors, Arm achieves lower latency and higher memory bandwidth, both critical for certain AI workloads that depend heavily on rapid data access.

Each chiplet uses an 8 by 9 coherent mesh interconnect that connects CPU cores, memory, I/O, and accelerators. This mesh incorporates 128MB of distributed system-level cache and hierarchical caching logic to optimize data movement across the die. The coherent mesh extends beyond individual dies, allowing Arm to maintain data coherency across both chiplets and even external systems. This approach resembles Intel’s Xeon architecture more closely than AMD’s distributed compute model with central I/O dies.

Memory System Capabilities

Arm engineered the AGI specifically with agentic AI systems and memory-intensive workloads in mind. The processor features two independent six-channel DDR5 memory controllers per chiplet, supporting memory speeds up to DDR5-8800. This dual-controller arrangement provides total memory bandwidth reaching 845 GB/s when both subsystems operate at maximum capacity. If a core accesses memory attached to the opposite chiplet, the request crosses the die-to-die connection with some latency penalty, but Arm’s design philosophy emphasizes providing maximum bandwidth per core.

The DDR5 memory controllers incorporate sophisticated features to maximize real-world performance. Fully out-of-order command scheduling allows flexible memory access patterns. Bank parallelism optimization and programmable page policies help extract effective bandwidth from the DRAM subsystem. Anti-starvation mechanisms prevent individual processes from monopolizing bandwidth, ensuring predictable service during heavy load conditions. Additional features include memory bandwidth limiting, quality-of-service traffic prioritization, and congestion feedback to manage contention when multiple cores and I/O devices compete for memory access.

Reliability features are equally comprehensive. The memory subsystem includes Chipkill-class error correction protecting against single DRAM device failures, automatic memory scrubbing, row-hammer mitigation, repair support, error injection capabilities, and extensive RAS error logging for diagnostics.

I/O and Connectivity

data center server racks
Photo by Taylor Vick

The AGI includes 96 PCIe 6.0 lanes with CXL 3.0 protocol support for memory expansion, four PCIe 4.0 lanes, and I3C, I2C, and SPI interfaces for various peripherals and management functions. The processor operates within a 300W thermal design power envelope, though real-world power consumption will depend on specific configurations and workload characteristics.

What This Means for Buyers

Arm’s emphasis on memory performance and low latency positions the AGI for specific workload categories rather than general-purpose computing dominance. Organizations running single-threaded applications, latency-sensitive services, or agentic AI systems may find significant value in this architecture. However, Arm has not released conventional benchmark data comparing the AGI directly against current AMD EPYC or Intel Xeon processors. The company’s only performance claim states 2X performance per rack versus latest x86 platforms based on estimates, which lacks the detail buyers typically need for purchasing decisions.

For data center managers, the AGI represents a genuine alternative to established architectures when it reaches market availability. The design choices reflect a different optimization philosophy than competitors, which may deliver superior results for particular workloads but could underperform on others. As the server market continues evolving, particularly with innovations in processor design accelerating across the industry, having diverse architectural options helps ensure infrastructure decisions match specific business requirements. Interested buyers should plan for detailed third-party testing and benchmarking once systems become available for evaluation.