IBM’s Breakthrough Dual ISA Processor Combines Two Computing Worlds

IBM has announced a significant advancement in mainframe CPU architecture with its new dual-ISA processor, marking the first time a single core can natively execute both Arm and z/Architecture instructions. Unveiled at Hot Chips 2026, this represents a fundamental shift in how enterprises can deploy software across mission-critical infrastructure.

The dual-ISA approach differs from traditional heterogeneous chip designs that combine separate Arm and x86 cores on the same die. Instead, IBM engineered a unified core that switches between instruction sets dynamically within nanoseconds, treating both Arm (AArch64) and z/Architecture as first-class computing citizens. This means Arm-based software runs natively without modification, eliminating the need to port applications specifically for mainframe environments.

Core Specifications and Performance Gains

circuit board microchip electronics
Photo by Sahand Babali

The new processor features 11 high-performance cores built on a 2nm manufacturing process, running at a base frequency of 5.7 GHz. This represents a solid upgrade from IBM’s current Telum II processor, which operates eight cores at up to 5.5 GHz. Beyond raw core count and clock speed, the architecture includes expanded cache hierarchies: 36 MB of private L2 cache, 432 MB of virtual L3, and 3.5 GB of virtual L4.

Each core supports simultaneous multithreading, enabling parallel execution across both instruction sets. The processor also maintains existing hardware accelerators for AI, compression, and cryptography workloads, ensuring backward compatibility while adding new capabilities for emerging workloads.

What This Means for Enterprise Buyers

The practical impact of dual-ISA execution is substantial for organizations running large-scale computing operations. Financial institutions, government agencies, and other enterprises that depend on mainframe reliability can now run modern Arm-based software without separate x86 or Arm servers. Desktop CPU Shipments Crash 20% YoY: What Buyers Need to Know shows that the broader CPU market faces challenges, but mainframe processors continue serving specialized, mission-critical roles.

IBM leverages a Linux Kernel-level Virtual Machine (KVM) to support AArch64 instructions while keeping standard z/Architecture code on the native execution path. This dual-track approach ensures mainframe uptime standards remain uncompromised. The company claims 99.999999% availability, translating to just 0.032 seconds of downtime annually.

AI Acceleration Gets Major Boost

Alongside the processor announcement, IBM revealed a next-generation AI accelerator with 16 cores optimized for newer artificial intelligence data formats, including FP4 and MXFP4. The accelerator ships with 96 GB of HBM3e memory, delivering up to 4 TB/s bandwidth, representing a 20x improvement over the previous LPDDR5-based design.

This memory upgrade addresses a critical bottleneck in AI workloads, where data throughput often limits performance more than raw compute power. Organizations running machine learning inference or training on mainframe infrastructure will benefit significantly from this bandwidth increase.

Architecture Deep Dive

server room infrastructure network
Photo by Tyler

IBM’s engineering team made substantial modifications to the core’s internal execution pipeline to support Arm instruction decoding. The branch prediction unit carries over Telum II’s existing design without changes, while the fetch engine uses virtual cache tags to reduce translation overhead. The dispatch stage repurposes existing register rename logic for Arm’s 32-register model.

In the arithmetic and load-store units, IBM reuses fundamental data flow operations where applicable, such as addition circuits. New hardware structures were added for Scalable Vector Extension (SVE) support and special floating-point data types like FP16. The translation engine incorporates a new page walk mechanism while reusing existing Translation Lookaside Buffer (TLB) infrastructure.

When to Expect These Systems

IBM traditionally introduces new mainframe systems every two and a half to three years. Based on current timelines, this dual-ISA processor will likely appear in the next-generation z18 mainframe series within the expected cycle. Real-world deployment depends heavily on individual enterprise requirements and upgrade schedules, as Intel Nova Lake CPU Power Draw Hits 296W illustrates how specialized processors target specific market segments with tailored performance characteristics.

For organizations currently running separate Arm and mainframe infrastructure, consolidation opportunities emerge with this architecture. The ability to unify software deployment across platforms while maintaining mainframe-grade reliability represents a meaningful efficiency gain, potentially reducing operational complexity and hardware footprint.

This advancement underscores IBM’s commitment to keeping mainframes relevant in an era where most software development targets Arm and x86 platforms. Rather than asking developers to port applications specifically for mainframe deployment, dual-ISA execution inverts the equation: mainframes can now run enterprise-standard software directly.